1. Field of the Invention
The invention relates to a semiconductor integrated circuit device in which semiconductor circuits consisting of CMOS elements and the like are integrated, and also to a method of fabricating the device.
2. Description of Related Art
FIG. 1 is a view showing a layout of a conventional semiconductor integrated circuit device in which a CMOS inverter is formed on a semiconductor substrate, and FIG. 2 is a sectional view taken along line II--II in FIG. 1. In the figures, numeral 1 designates a P-type semiconductor substrate, and an N-well 2 is formed in a region of the P-type semiconductor substrate 1 where a P-channel transistor 21 is to be formed. An N-type diffusion layer 10 which is for the efficient connection of a Vcc conductor 3 formed thereon with the N-well 2, is formed in the left portion of the N-well 2 in FIG. 2. A P-type diffusion layer 5 of the P-channel transistor 21 is formed on the right of the N-type diffusion layer 10.
In FIG. 2, an N-type diffusion layer 6 of an N-channel transistor 22 is formed at an appropriate position of the P-type semiconductor substrate 1 where the N-well 2 is not formed. A P-type diffusion layer 11, which is for the efficient connection of a Vss conductor 4 formed thereon with the P-type semiconductor substrate 1, is formed on the right of the N-type diffusion layer 6. An insulating film 16 is formed in surface regions where the N-type diffusion layer 10, the P-type diffusion layer 5, the N-type diffusion layer 6, and the P-type diffusion layer 11 are not formed. An insulating layer 15 is formed on the insulating film 16. The Vcc conductor 3 is connected to the N-type diffusion layer 10 and the P-type diffusion layer 5 through the contact holes 9. The Vss conductor 4 is connected to the N-type diffusion layer 6 and the P-type diffusion layer 11 through the contact holes 9.
In FIG. 1, the reference numeral 7 designates a gate for the P-channel transistor 21 and the N-channel transistor 22. The gate is made of polysilicon. The reference numeral 8 designates an output conductor for connecting both drains of the P-channel transistor 21 and the N-channel transistor 22. The output conductor is made of aluminum. Both of the drain regions are connected to the output conductor 8 through contact holes 9.
A method of fabricating the conventional semiconductor integrated circuit device thus configured will be described. First, in a design process, N-well data are previously input as the design data into the region where the P-channel transistor 21 is to be formed, and a mask, for forming the N-well 2 in the portion where the N-well data exist, is fabricated. The N-well 2 is then formed using the mask. Thereafter, conventional fabrication processes are conducted to fabricate the P-channel transistor 21 in the region where the P-channel transistor 21 is to be formed and the N-well 2 is formed, and the N-channel transistor 22 is fabricated in the region where the N-channel transistor 22 is to be formed and the N-well 2 is not formed.
FIG. 3 is a sectional view showing the structure of another conventional semiconductor integrated circuit device which has the PN double well structure. In a low-concentration P-type semiconductor substrate 19, the N-well 2 is formed in the region where a P-channel transistor 21 is to be formed, and a P-well 18 in the region where the N-channel transistor 22 is to be formed. The other portions are configured in the same manner as those of FIG. 2.
In the thus configured semiconductor integrated circuit device, N-well data are previously input as the design data into the region where the P-channel transistor 21 is to be formed, and P-well data are previously input as the design data into the region where the N-channel transistor 22 is to be formed. The N-well 2 and the P-well 18 are formed on the basis of these deign data. In the same manner as the case described above, thereafter, elements are fabricated by conventional fabrication processes.
In the conventional semiconductor integrated circuit device mentioned above, the N-well 2 is formed only in the region of the P-type semiconductor substrate 1 where the P-channel transistor 21 is to be formed, and an inverter is formed which has the P-channel transistor 21 and the N-channel transistor 22 between Vcc and Vss. In this case, the N-well 2 is formed only in a part of the P-type semiconductor substrate 1 (for example, 1/4 to 1/3 of the substrate), and hence the junction area is small, and so is the PN junction capacitance 17 between the P-type semiconductor substrate 1 and the N-well 2.
When a noise is fabricated in the Vcc conductor 3 or the Vss conductor 4 of the semiconductor integrated circuit device having the small PN junction capacitance 17, the potential variation of the Vcc conductor 3 or the Vss conductor 4 is hardly absorbed so that a malfunction easily occurs in the circuits. Such a phenomenon appears not only in the N-well system shown in FIGS. 1 and 2 but also in the P, N double well system shown in FIG. 3.
Known techniques to solve the problem mentioned above include the followings:
Japanese Patent Application Laid-Open No. 57-211741 (1982) discloses a semiconductor device wherein a semiconductor region of a conductivity type opposite to that of a semiconductor substrate is formed immediately under a bonding pad in order to form a parasitic capacitance for suppressing a noise level.
Japanese Patent Application Laid-Open No. 59-117148 (1984) discloses a semiconductor integrated circuit device wherein a power supply conductor is connected to a semiconductor substrate and also to a semiconductor region which forms a PN junction with the semiconductor substrate, thereby reducing an influence of a noise.
Japanese Patent Application Laid-Open No. 3-32052(1991) discloses a semiconductor integrated circuit device wherein a diffusion capacitance between a source/drain diffusion region and a well diffusion region is formed in the conductor regions and the diffusion capacitance is connected to a power supply conductor or a ground conductor, whereby a noise is relaxed and a circuit is prevented from malfunctioning.
Japanese Patent Application laid-Open No. 2-153562 (1990) discloses a CMOS integrated circuit wherein, an N-type (or P-type) diffusion layer which is selectively formed in a P-type (or N-type) semiconductor substrate and is connected to a power supply conductor or a ground conductor, or a P-type (or N-type) diffusion layer which is selectively formed in a N-type (or P-type) well and is connected to the power supply conductor or the ground conductor, is disposed in a conductor region in order to reduce an influence of a noise appearing in the power supply conductor or the ground conductor.